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» A Simulator for the Reconfigurable Mesh Architecture
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ICS
2005
Tsinghua U.
15 years 3 months ago
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
Given the importance of parallel mesh generation in large-scale scientific applications and the proliferation of multilevel SMTbased architectures, it is imperative to obtain ins...
Christos D. Antonopoulos, Xiaoning Ding, Andrey N....
GPEM
2002
163views more  GPEM 2002»
14 years 9 months ago
Fast Ant Colony Optimization on Runtime Reconfigurable Processor Arrays
Ant Colony Optimization (ACO) is a metaheuristic used to solve combinatorial optimization problems. As with other metaheuristics, like evolutionary methods, ACO algorithms often sh...
Daniel Merkle, Martin Middendorf
69
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INFOCOM
2007
IEEE
15 years 3 months ago
A Performance Study of Deployment Factors in Wireless Mesh Networks
Abstract— We present a measurement-parameterized performance study of deployment factors in wireless mesh networks using three performance metrics: client coverage area, backhaul...
Joshua Robinson, Edward W. Knightly
NOCS
2009
IEEE
15 years 4 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
86
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FPL
2007
Springer
120views Hardware» more  FPL 2007»
15 years 3 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano