188 search results - page 14 / 38 » A Simulator for the Reconfigurable Mesh Architecture |
IJES
2006
14 years 9 months ago
2006
: We present efficient solutions for the non-contiguous linear placement of data-paths for reconfigurable fabrics. A strip-based architecture is assumed for the reconfigurable fabr...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
INFOCOM
2005
IEEE
15 years 3 months ago
2005
IEEE
— Even though multiple non-overlapped channels exist in the 2.4GHz and 5GHz spectrum, most IEEE 802.11-based multi-hop ad hoc networks today use only a single channel. As a resul...
VLSISP
2008
14 years 9 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
VLSISP
2008
14 years 9 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...