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» A Simulator for the Reconfigurable Mesh Architecture
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ERSA
2010
199views Hardware» more  ERSA 2010»
14 years 7 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 4 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
DAC
2003
ACM
15 years 2 months ago
4G terminals: how are we going to design them?
Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targe...
Jan Craninckx, Stéphane Donnay
ICC
2008
IEEE
139views Communications» more  ICC 2008»
15 years 4 months ago
Practical Routing and Channel Assignment Scheme for Mesh Networks with Directional Antennas
Abstract— Wireless Mesh Network (WMN) has been recognized as one of the promising technologies to provide wireless broadband access. In addition to the multi-radio multi-channel ...
Wei Zhou, Xi Chen, Daji Qiao
ISPASS
2008
IEEE
15 years 4 months ago
Program Phase Detection based on Critical Basic Block Transitions
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
Paruj Ratanaworabhan, Martin Burtscher