Sciweavers

    188 search results - page 31 / 38
    » A Simulator for the Reconfigurable Mesh Architecture
    Sort
    View
    67
    Voted
    DAC
    2008
    ACM
    145views Computer Architecture» more  DAC 2008»
    Enhancing timing-driven FPGA placement for pipelined netlists
    15 years 10 months ago
    Enhancing timing-driven FPGA placement for pipelined netlists
    Download  www.ee.washington.edu
    FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
    Kenneth Eguro, Scott Hauck
    claim paper
    Read More »
    ESTIMEDIA
    2004
    Springer
    133views Multimedia» more  ESTIMEDIA 2004»
    Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia comm
    15 years 1 months ago
    Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia comm
    Download  www.ee.ust.hk
    This paper presents a new adaptive scheme to reduce the computation energy of the discrete cosine transform (DCT) architecture for image/video coding. The scheme employs the noise ...
    Feng Liu, Chi-Ying Tsui
    claim paper
    Read More »
    BIBE
    2007
    IEEE
    126views Bioinformatics» more  BIBE 2007»
    FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data
    14 years 11 months ago
    FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data
    Download  www.cse.sc.edu
    In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
    Jason D. Bakos, Panormitis E. Elenis, Jijun Tang
    claim paper
    Read More »
    ICCAD
    2003
    IEEE
    123views Hardware» more  ICCAD 2003»
    The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
    15 years 6 months ago
    The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
    Download  cseweb.ucsd.edu
    The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
    Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
    claim paper
    Read More »
    FPGA
    2006
    ACM
    195views FPGA» more  FPGA 2006»
    An adaptive Reed-Solomon errors-and-erasures decoder
    15 years 1 months ago
    An adaptive Reed-Solomon errors-and-erasures decoder
    Download  www.ecs.umass.edu
    The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
    Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2025, USA.