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» A Simulator for the Reconfigurable Mesh Architecture
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PC
2010
177views Management» more  PC 2010»
14 years 8 months ago
Parallel graph component labelling with GPUs and CUDA
Graph component labelling, which is a subset of the general graph colouring problem, is a computationally expensive operation that is of importance in many applications and simula...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne
86
Voted
CASES
2008
ACM
14 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 3 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
CN
2000
67views more  CN 2000»
14 years 9 months ago
SPREAD: Scalable platform for reliable and efficient automated distribution
We introduce SPREAD - a new architecture for distributing and maintaining up-to-date Web content that simultaneously employs three different mechanisms: client validation, server ...
Pablo Rodriguez, Sandeep Sibal
JNSM
2010
110views more  JNSM 2010»
14 years 4 months ago
Distributed Automatic Configuration of Complex IPsec-Infrastructures
The Internet Protocol Security Architecture IPsec is hard to deploy in large, nested, or dynamic scenarios. The major reason for this is the need for manual configuration of the cr...
Michael Rossberg, Guenter Schaefer, Thorsten Struf...