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FTCS
1998
79views more  FTCS 1998»
14 years 11 months ago
Proving Correctness of a Controller Algorithm for the RAID Level 5 System
Most RAID controllers implemented in industry are complicated and di cult to reason about. This complexity has led to software and hardware systems that are di cult to debug and h...
Mandana Vaziri, Nancy A. Lynch, Jeannette M. Wing
CODES
2005
IEEE
15 years 3 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
15 years 4 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
MIDDLEWARE
2007
Springer
15 years 3 months ago
Promoting levels of openness on component-based adaptable middleware
It is widely accepted that middleware is an important architectural element which facilitates the development of software systems. In this paper we propose a novel approach for de...
Tarcisio da Rocha, Anna-Brith Arntsen, Arne Ketil ...
ICCBSS
2005
Springer
15 years 3 months ago
Resolving Architectural Mismatches of COTS Through Architectural Reconciliation
Abstract. The integration of COTS components into a system under development entails architectural mismatches. These have been tackled, so far, at the component level, through comp...
Paris Avgeriou, Nicolas Guelfi