601 search results - page 40 / 121 » A Simulink(c)-Based Approach to System Level Design and Arch... |
DFT
1999
IEEE
15 years 2 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
103
click to vote
ERSA
2009
14 years 7 months ago
2009
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
RCC
2002
14 years 9 months ago
2002
In recent years Arvind's Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specifi...
CDES
2008
14 years 11 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...