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FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
15 years 2 months ago
A FPGA-Based Implementation of a Fault-Tolerant Neural Architecture for Photon Identification
Event identification in photon counting ICCD detectors requires a high level image analysis which cannot be easily described algorithmically: neural networks are promising to appr...
Monica Alderighi, E. L. Gummati, Vincenzo Piuri, G...
DATE
2004
IEEE
109views Hardware» more  DATE 2004»
15 years 1 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
15 years 4 months ago
A self-adaptive system architecture to address transistor aging
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...
Omer Khan, Sandip Kundu
BMCBI
2005
98views more  BMCBI 2005»
14 years 9 months ago
Iterative approach to model identification of biological networks
Background: Recent advances in molecular biology techniques provide an opportunity for developing detailed mathematical models of biological processes. An iterative scheme is intr...
Kapil G. Gadkar, Rudiyanto Gunawan, Francis J. Doy...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 3 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane