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FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 5 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
SEM
2004
Springer
15 years 4 months ago
Experience with Lightweight Distributed Component Technologies in Business Intelligence Systems
Business Intelligence (BI) systems address the demands of large scale enterprises for operational analytics, management information and decision support tasks. Building such applic...
Leticia Duboc, Tony Wicks, Wolfgang Emmerich
94
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CODES
2006
IEEE
15 years 2 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
SIGPLAN
2008
14 years 11 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
GPCE
2009
Springer
15 years 2 months ago
Mapping problem-space to solution-space features: a feature interaction approach
Mapping problem-space features into solution-space features is a fundamental configuration problem in software product line engineering. A configuration problem is defined as g...
Frans Sanen, Eddy Truyen, Wouter Joosen