1312 search results - page 206 / 263 » A Software Process Scheduling Simulator |
106
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CGO
2003
IEEE
15 years 3 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
CODES
1999
IEEE
15 years 2 months ago
1999
IEEE
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
CASES
2005
ACM
14 years 12 months ago
2005
ACM
Dynamic frequency scaling and dynamic voltage scaling have been developed to save power and/or energy for general purpose computing platforms and high-end embedded systems. This p...
124
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SIGOPS
2010
14 years 4 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...