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VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
15 years 10 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
14 years 11 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
15 years 6 months ago
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs
A fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-todigital converters (ADCs) in the presence of circuit nonidealities ...
Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei
TVLSI
2008
176views more  TVLSI 2008»
14 years 9 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
DAC
2004
ACM
15 years 10 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen