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GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
ETS
2006
IEEE
100views Hardware» more  ETS 2006»
15 years 3 months ago
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun,...
TCAD
2008
136views more  TCAD 2008»
14 years 9 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
ICCAD
1994
IEEE
92views Hardware» more  ICCAD 1994»
15 years 1 months ago
Synthesis of manufacturable analog circuits
? We describe a synthesis system that takes operating range constraints and inter- and intra- circuit parametric manufacturing variations into account while designing a sized and b...
Tamal Mukherjee, L. Richard Carley, Rob A. Rutenba...
ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
15 years 6 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh