57 search results - page 8 / 12 » A Statistical Approach to the Timing-Yield Optimization of P... |
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
72
Voted
FPL
2005
Springer
15 years 3 months ago
2005
Springer
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
78
Voted
HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
ICCAD
1991
IEEE
15 years 1 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...