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SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
15 years 5 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
15 years 4 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
DAC
1991
ACM
15 years 3 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang
DAC
2006
ACM
15 years 5 months ago
Modeling and analysis of circuit performance of ballistic CNFET
With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-ana...
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Tho...
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
15 years 6 months ago
Signal Probability Based Statistical Timing Analysis
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
Bao Liu