340 search results - page 17 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
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GLVLSI
2010
IEEE
15 years 4 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
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ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
VLSI
2007
Springer
15 years 5 months ago
2007
Springer
System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it ...
ISCAS
2005
IEEE
15 years 5 months ago
2005
IEEE
Abstract— Time encoding is a mechanism for representing the information contained in a continuous time, bandlimited, analog signal as the zero-crossings of a binary signal. Time ...