Sciweavers

340 search results - page 18 / 68
» A Statistical Performance Simulation Methodology for VLSI Ci...
Sort
View
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
15 years 8 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
16 years 4 months ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
DFT
2007
IEEE
109views VLSI» more  DFT 2007»
15 years 10 months ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 9 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ANSS
2005
IEEE
15 years 10 months ago
The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation
When performed on a classical computer, the simulation of quantum circuits is usually an exponential job. The methodology based on Hardware Description Languages is able to isolat...
Mihai Udrescu, Lucian Prodan, Mircea Vladutiu