340 search results - page 21 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
105
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IOLTS
2005
IEEE
15 years 5 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
117
Voted
GLVLSI
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
104
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PARLE
1987
1987
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
15 years 3 months ago
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
VLSID
2000
IEEE
15 years 4 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
70
Voted
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...