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» A Statistical Performance Simulation Methodology for VLSI Ci...
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DAC
2003
ACM
16 years 22 days ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
CODES
2008
IEEE
14 years 12 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
75
Voted
DAC
2000
ACM
15 years 4 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
95
Voted
DAC
2005
ACM
16 years 22 days ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
15 years 3 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik