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GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
15 years 1 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
SBCCI
2006
ACM
97views VLSI» more  SBCCI 2006»
15 years 5 months ago
An ultra low-power class-AB sinh integrator
A new ultra low-power Class-AB Sinh integrator is proposed here. The translinear companding integrator is based on hyperbolic-sine transconductors and uses only one grounded capac...
Sandro A. P. Haddad, Wouter A. Serdijn
VLSID
1997
IEEE
399views VLSI» more  VLSID 1997»
15 years 4 months ago
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
Pradip Mandal, V. Visvanathan
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
15 years 8 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
15 years 6 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...