340 search results - page 31 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
129
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VLSID
2004
IEEE
16 years 2 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
VLSID
2004
IEEE
16 years 2 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
106
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ISCAS
1999
IEEE
15 years 6 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
95
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ICCAD
2006
IEEE
15 years 11 months ago
2006
IEEE
Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-...
VLSI
2010
Springer
14 years 8 months ago
2010
Springer
A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation...