340 search results - page 35 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
IEEEPACT
2003
IEEE
15 years 5 months ago
2003
IEEE
Recent work has shown that multithreaded workloads running in execution-driven, full-system simulation environments cannot use instructions per cycle (IPC) as a valid performance ...
DAC
2006
ACM
15 years 3 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
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DATE
2005
IEEE
15 years 1 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
DAC
2005
ACM
16 years 23 days ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...