340 search results - page 38 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
DAC
2003
ACM
15 years 5 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
GLOBECOM
2010
IEEE
14 years 9 months ago
2010
IEEE
In this paper we formulate a power loading problem for the spatial subchannels (parallel channels) of a single-carrier MIMO-SVD system. The power loading solution is designed to mi...
VTS
2003
IEEE
15 years 5 months ago
2003
IEEE
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
DAC
2007
ACM
15 years 3 months ago
2007
ACM
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...