340 search results - page 40 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
VLSID
2000
IEEE
15 years 4 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
108
click to vote
DAC
2010
ACM
15 years 14 hour ago
2010
ACM
With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to cope with the prominent process variation and to incr...
GLVLSI
2009
IEEE
15 years 6 months ago
2009
IEEE
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...