340 search results - page 63 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
129
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
140
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DAC
2001
ACM
16 years 5 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
131
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ASYNC
2002
IEEE
15 years 9 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
124
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FCCM
2003
IEEE
15 years 9 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
145
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...