340 search results - page 9 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
108
click to vote
TVLSI
2008
14 years 11 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
DAC
2004
ACM
16 years 21 days ago
2004
ACM
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
81
Voted
ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
VLSID
2004
IEEE
16 years 3 days ago
2004
IEEE
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
ISQED
2002
IEEE
15 years 4 months ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...