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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ANSOFT
1999
74views more  ANSOFT 1999»
15 years 4 months ago
On Coping with Real-Time Software Dynamic Inconsistency by Built-in Tests
In real-time systems, dynamic inconsistencies of software are hardly detected, diagnosed and handled. A built-in test (BIT) method is developed to cope with software dynamic incon...
Yingxu Wang, Graham King, Dilip Patel, Shushma Pat...
WOTUG
2008
15 years 5 months ago
Representation and Implementation of CSP and VCR Traces
Abstract. Communicating Sequential Processes (CSP) was developed around a formal algebra of processes and a semantics based on traces (and failures and divergences). A trace is a r...
Neil C. C. Brown, Marc L. Smith
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
15 years 10 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner
IFIP
2010
Springer
14 years 11 months ago
Reasoning about Probabilistic Security Using Task-PIOAs
Abstract. Task-structured probabilistic input/output automata (taskPIOAs) are concurrent probabilistic automata that, among other things, have been used to provide a formal framewo...
Aaron D. Jaggard, Catherine Meadows, Michael Mislo...