641 search results - page 9 / 129 » A Study in Coverage-Driven Test Generation |
FATES
2003
Springer
15 years 5 months ago
2003
Springer
Use of model-checking approaches for test generation from requirement models have been proposed by several researchers. These approaches leverage the witness (or counter-example) ...
ITC
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
EURODAC
1994
IEEE
15 years 3 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
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SEUS
2010
IEEE
14 years 10 months ago
2010
IEEE
Chilenski and Miller [1] claim that the error detection probability of a test set with full modified condition/decision coverage (MC/DC) on the system under test converges to 100%...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...