Sciweavers

155 search results - page 23 / 31
» A Study of E-learning Architecture Based on Knowledge Innova...
Sort
View
EJWCN
2010
162views more  EJWCN 2010»
14 years 4 months ago
OMNeT++-Based Cross-Layer Simulator for Content Transmission over Wireless Ad Hoc Networks
Flexbility and deployment simplicity are among the numerous advantages of wireless links when compared to standard wired communications. However, challenges do remain high for wire...
Raphaël Massin, Catherine Lamy-Bergot, Christ...
HPDC
2006
IEEE
15 years 3 months ago
Path Grammar Guided Trace Compression and Trace Approximation
Trace-driven simulation is an important technique used in the evaluation of computer architecture innovations. However using it for studying parallel computers and applications is...
Xiaofeng Gao, Allan Snavely, Larry Carter
99
Voted
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 1 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
BMCBI
2010
202views more  BMCBI 2010»
14 years 9 months ago
NeMo: Network Module identification in Cytoscape
Background: As the size of the known human interactome grows, biologists increasingly rely on computational tools to identify patterns that represent protein complexes and pathway...
Corban G. Rivera, Rachit Vakil, Joel S. Bader
ICC
2007
IEEE
114views Communications» more  ICC 2007»
15 years 3 months ago
An FPGA Implementation of Dirty Paper Precoder
—Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We stud...
Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan ...