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» A Study of Energy Saving in Customizable Processors
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IPCCC
2006
IEEE
14 years 8 days ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
HPCA
2005
IEEE
14 years 6 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 3 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
TPDS
2008
122views more  TPDS 2008»
13 years 6 months ago
Nonmigratory Multiprocessor Scheduling for Response Time and Energy
Energy usage has been an important concern in recent research on online job scheduling, where processors are allowed to vary the speed dynamically so as to save energy whenever pos...
Tak Wah Lam, Lap-Kei Lee, Isaac Kar-Keung To, Prud...
CASES
2004
ACM
13 years 11 months ago
Reducing both dynamic and leakage energy consumption for hard real-time systems
While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for t...
Linwei Niu, Gang Quan