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» A Study of Practical Deduplication
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DAC
2009
ACM
15 years 11 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2007
ACM
15 years 11 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
DAC
2007
ACM
15 years 11 months ago
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution
It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. An important design constraint in suc...
Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi,...
SIGSOFT
2008
ACM
15 years 10 months ago
Semi-automating small-scale source code reuse via structural correspondence
Developers perform small-scale reuse tasks to save time and to increase the quality of their code, but due to their small scale, the costs of such tasks can quickly outweigh their...
Rylan Cottrell, Robert J. Walker, Jörg Denzin...
SIGSOFT
2003
ACM
15 years 10 months ago
Regression testing of GUIs
Although graphical user interfaces (GUIs) constitute a large part of the software being developed today and are typically created using rapid prototyping, there are no effective r...
Atif M. Memon, Mary Lou Soffa