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FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 2 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
DATE
2008
IEEE
130views Hardware» more  DATE 2008»
14 years 11 months ago
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications
This paper presents the implementation of a dualpriority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkern...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
FPGA
2010
ACM
197views FPGA» more  FPGA 2010»
15 years 22 days ago
A 3d-audio reconfigurable processor
Various multimedia communication systems based on 3DAudio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in t...
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi G...
FPL
2010
Springer
139views Hardware» more  FPL 2010»
14 years 7 months ago
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
ISCAS
2007
IEEE
176views Hardware» more  ISCAS 2007»
15 years 3 months ago
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier
— Simple Power Analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms ca...
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Ak...