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ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
15 years 3 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ASAP
2007
IEEE
203views Hardware» more  ASAP 2007»
15 years 1 months ago
Reconfigurable Universal Adder
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
OSN
2011
14 years 7 days ago
A parallel iterative scheduler for asynchronous Optical Packet Switching networks
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...
Pablo Pavón-Mariño, M. Victoria Buen...
CAV
2010
Springer
192views Hardware» more  CAV 2010»
15 years 1 months ago
Invariant Synthesis for Programs Manipulating Lists with Unbounded Data
We address the issue of automatic invariant synthesis for sequential programs manipulating singly-linked lists carrying data over infinite data doe define for that a framework ba...
Ahmed Bouajjani, Cezara Dragoi, Constantin Enea, A...
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
15 years 2 months ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...