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» A Survey of QoS Architectures
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GLOBECOM
2006
IEEE
15 years 3 months ago
A Practical Switch-Memory-Switch Architecture Emulating PIFO OQ
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
Nan Hua, Yang Xu, Peng Wang, Depeng Jin, Lieguang ...
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
14 years 1 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
15 years 4 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
CORR
2010
Springer
224views Education» more  CORR 2010»
14 years 10 months ago
A Cluster Based Replication Architecture for Load Balancing in Peer-to-Peer Content Distribution
In P2P systems, large volumes of data are declustered naturally across a large number of peers. But it is very difficult to control the initial data distribution because every use...
S. Ayyasamy, S. N. Sivanandam
IISWC
2006
IEEE
15 years 3 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...