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FDL
2004
IEEE
13 years 10 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
FDL
2007
IEEE
13 years 10 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
TVLSI
2002
130views more  TVLSI 2002»
13 years 5 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
ICSE
2007
IEEE-ACM
14 years 6 months ago
Plug-and-Play Architectural Design and Verification
Abstract. In software architecture, components represent the computational units of a system and connectors represent the interactions among those units. Making decisions about the...
Shangzhu Wang, George S. Avrunin, Lori A. Clarke
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita