209 search results - page 1 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
58
Voted
ICCAD
1991
IEEE
15 years 1 months ago
1991
IEEE
78
Voted
DFT
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
GLVLSI
2003
IEEE
15 years 3 months ago
2003
IEEE
94
Voted
ICCAD
2002
IEEE
15 years 7 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
93
Voted
DAC
1991
ACM
15 years 1 months ago
1991
ACM
-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...