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ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
15 years 2 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
DATE
2009
IEEE
167views Hardware» more  DATE 2009»
15 years 4 months ago
Analyzing the impact of process variations on parametric measurements: Novel models and applications
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
Sherief Reda, Sani R. Nassif
ARC
2010
Springer
183views Hardware» more  ARC 2010»
14 years 9 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
ICMCS
2006
IEEE
142views Multimedia» more  ICMCS 2006»
15 years 3 months ago
Tricodes: A Barcode-Like Fiducial Design for Augmented Reality Media
Visual markers, or fiducials, have become one of the most common methods of camera pose estimation in Augmented Reality (AR) media. Many present day fiducial-based AR systems us...
Jonathan Mooser, Suya You, Ulrich Neumann
58
Voted
MICRO
2007
IEEE
71views Hardware» more  MICRO 2007»
14 years 9 months ago
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
Design complexity is rapidly becoming a limiting factor in the design of modern, high-performance microprocessors. This paper introduces an optimization technique to improve the e...
Francisco J. Mesa-Martinez, Jose Renau