We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Visual markers, or fiducials, have become one of the most common methods of camera pose estimation in Augmented Reality (AR) media. Many present day fiducial-based AR systems us...
Design complexity is rapidly becoming a limiting factor in the design of modern, high-performance microprocessors. This paper introduces an optimization technique to improve the e...