12 search results - page 1 / 3 » A Temporal Assertion Extension to Verilog |
73
Voted
ATVA
2004
Springer
15 years 4 months ago
2004
Springer
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Te...
ICALP
2009
Springer
15 years 11 months ago
2009
Springer
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
103
Voted
ACTA
2010
14 years 11 months ago
2010
The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL an...
87
Voted
FMCAD
2008
Springer
15 years 12 days ago
2008
Springer
The semantics of temporal logic is usually defined with respect to a word representing a computation path over a set of atomic propositions. A temporal logic formula does not contr...
106
click to vote
SPIN
2000
Springer
15 years 2 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...