Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) so...
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating ...
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...
Abstract. Combinatorial auctions are an important e-commerce application where bidders can bid on combinations of items. The problem of selecting the best bids that cover all items...
Use of model-checking approaches for test generation from requirement models have been proposed by several researchers. These approaches leverage the witness (or counter-example) ...
Mats Per Erik Heimdahl, Sanjai Rayadurgam, Willem ...