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» A Temporal Logic of Robustness
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ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
15 years 5 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
TCAD
1998
126views more  TCAD 1998»
15 years 1 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 8 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ICC
2007
IEEE
100views Communications» more  ICC 2007»
15 years 8 months ago
Service Delivery in Collaborative Context-Aware Environments Using Fuzzy Logic
— This paper illustrates a novel decision making algorithm to deliver telecommunication services that match in the best possible way end-user’s requirements to current environm...
Raffaele Giaffreda, Javier A. Barria
133
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ISCC
2006
IEEE
202views Communications» more  ISCC 2006»
15 years 7 months ago
Fuzzy Logic Congestion Control in TCP/IP Tandem Networks
Network resource management and control is a complex problem that requires robust, possibly intelligent, control methodologies to obtain satisfactory performance. While many Activ...
Chrysostomos Chrysostomou, Andreas Pitsillides