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IPPS
1998
IEEE
15 years 4 months ago
A Java Development and Runtime Environment for Reconfigurable Computing
Fast runtime reconfigurable hardware enables system designers to swap hardware into and out of an FPGA much as the pages of virtual memory are swapped into and out of virtual memor...
Don Davis, Michael Barr, Toby Bennett, Stephen Edw...
SIGIR
2005
ACM
15 years 5 months ago
Indexing emails and email threads for retrieval
Electronic mail poses a number of unusual challenges for the design of information retrieval systems and test collections, including informal expression, conversational structure,...
Yejun Wu, Douglas W. Oard
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
15 years 3 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
76
Voted
WOTUG
2007
15 years 28 days ago
C++CSP2: A Many-to-Many Threading Model for Multicore Architectures
Abstract. The advent of mass-market multicore processors provides exciting new opportunities for parallelism on the desktop. The original C++CSP – a library providing concurrency...
Neil Brown
IPPS
2009
IEEE
15 years 6 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...