499 search results - page 14 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
DAC
2010
ACM
15 years 1 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
A recursive algorithm for solving Boolean relations is presented. It provides several features: wide exploration of solutions, parametrizable cost function and efficiency. The exp...
GLVLSI
2007
IEEE
14 years 11 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...