499 search results - page 16 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
130
Voted
CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
119
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DAC
2007
ACM
16 years 3 months ago
2007
ACM
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
238
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DAC
2011
ACM
14 years 2 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
124
Voted
DAC
2003
ACM
15 years 7 months ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
113
Voted
ISQED
2005
IEEE
15 years 8 months ago
2005
IEEE
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...