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» A Three-Phase Algorithm for Computer Aided siRNA Design
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ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
15 years 3 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
DAC
2006
ACM
15 years 10 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DAC
2010
ACM
15 years 24 days ago
Electronic design automation for social networks
Online social networks are a growing internet phenomenon: they connect millions of individuals through sharing of common interests, political and religious views, careers, etc. So...
Andrew DeOrio, Valeria Bertacco
DAC
2005
ACM
14 years 11 months ago
On the need for statistical timing analysis
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...
Farid N. Najm
GECCO
2007
Springer
187views Optimization» more  GECCO 2007»
15 years 3 months ago
Defining implicit objective functions for design problems
In many design tasks it is difficult to explicitly define an objective function. This paper uses machine learning to derive an objective in a feature space based on selected examp...
Sean Hanna