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» A Three-Phase Algorithm for Computer Aided siRNA Design
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DAC
2004
ACM
15 years 8 months ago
A new state assignment technique for testing and low power
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....
DAC
2007
ACM
16 years 3 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
DAC
2008
ACM
16 years 3 months ago
Formal datapath representation and manipulation for implementing DSP transforms
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
Franz Franchetti, James C. Hoe, Markus Püsche...
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 8 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
DAC
2005
ACM
16 years 3 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma