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» A Three-Phase Algorithm for Computer Aided siRNA Design
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ISPD
2006
ACM
71views Hardware» more  ISPD 2006»
15 years 8 months ago
Satisfying whitespace requirements in top-down placement
In this invited note we outline several algorithms and features appearing in Capo 10, free open-source software for congestion-driven standard cell placement, mixed-size placement...
Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L....
DAC
2010
ACM
15 years 6 months ago
An AIG-Based QBF-solver using SAT for preprocessing
In this paper we present a solver for Quantified Boolean Formulas (QBFs) which is based on And-Inverter Graphs (AIGs). We use a new quantifier elimination method for AIGs, which...
Florian Pigorsch, Christoph Scholl
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
16 years 3 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
SIGGRAPH
1995
ACM
15 years 6 months ago
Automatic reconstruction of surfaces and scalar fields from 3D scans
We present an efficient and uniform approach for the automatic reconstruction of surfaces of CAD (computer aided design) models and scalar fields defined on them, from an unorg...
Chandrajit L. Bajaj, Fausto Bernardini, Guoliang X...
DAC
2004
ACM
16 years 3 months ago
A method to decompose multiple-output logic functions
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...
Tsutomu Sasao, Munehiro Matsuura