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» A Three-Phase Algorithm for Computer Aided siRNA Design
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DAC
2002
ACM
16 years 3 months ago
River PLAs: a regular circuit structure
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
Fan Mo, Robert K. Brayton
DAC
2003
ACM
16 years 3 months ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
DAC
2005
ACM
16 years 3 months ago
Net weighting to reduce repeater counts during placement
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
Brent Goplen, Prashant Saxena, Sachin S. Sapatneka...
DAC
2005
ACM
16 years 3 months ago
Efficient SAT solving: beyond supercubes
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
Domagoj Babic, Jesse D. Bingham, Alan J. Hu
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 11 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata