499 search results - page 53 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
126
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DAC
2003
ACM
16 years 3 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
125
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CODES
2006
IEEE
15 years 6 months ago
2006
IEEE
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
115
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DAC
2006
ACM
15 years 8 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
151
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CODES
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
114
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VIS
2005
IEEE
16 years 3 months ago
2005
IEEE
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulatio...