499 search results - page 61 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
116
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DAC
2008
ACM
16 years 3 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
104
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DAC
2007
ACM
16 years 3 months ago
2007
ACM
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
105
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DAC
2003
ACM
16 years 3 months ago
2003
ACM
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
122
Voted
ISPD
2010
ACM
15 years 9 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
105
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ISPD
2004
ACM
15 years 7 months ago
2004
ACM
Many current designs contain a large number of standard cells intermixed with larger macro blocks. The range of size in these “mixed block” designs complicates the placement p...