499 search results - page 83 / 100 » A Three-Phase Algorithm for Computer Aided siRNA Design |
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
FMCAD
2007
Springer
15 years 1 months ago
2007
Springer
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
107
Voted
DAC
2004
ACM
15 years 1 months ago
2004
ACM
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...