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HPCA
2003
IEEE
16 years 2 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
EUROPAR
2005
Springer
15 years 7 months ago
An Approach to Performance Prediction for Parallel Applications
Abstract. Accurately modeling and predicting performance for largescale applications becomes increasingly difficult as system complexity scales dramatically. Analytic predictive mo...
Engin Ipek, Bronis R. de Supinski, Martin Schulz, ...
ICCS
2004
Springer
15 years 7 months ago
Using Runtime Measurements and Historical Traces for Acquiring Knowledge in Parallel Applications
Abstract. A new approach for acquiring knowledge of parallel applications regarding resource usage and for searching similarity on workload traces is presented. The main goal is to...
Luciano José Senger, Marcos José San...
DATE
2010
IEEE
169views Hardware» more  DATE 2010»
15 years 7 months ago
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
Daniele Ludovici, Alessandro Strano, Georgi Nedelt...
112
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SIGMETRICS
2008
ACM
161views Hardware» more  SIGMETRICS 2008»
15 years 1 months ago
Bound analysis of closed queueing networks with workload burstiness
Burstiness and temporal dependence in service processes are often found in multi-tier architectures and storage devices and must be captured accurately in capacity planning models...
Giuliano Casale, Ningfang Mi, Evgenia Smirni