As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Abstract. Accurately modeling and predicting performance for largescale applications becomes increasingly difficult as system complexity scales dramatically. Analytic predictive mo...
Engin Ipek, Bronis R. de Supinski, Martin Schulz, ...
Abstract. A new approach for acquiring knowledge of parallel applications regarding resource usage and for searching similarity on workload traces is presented. The main goal is to...
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
Daniele Ludovici, Alessandro Strano, Georgi Nedelt...
Burstiness and temporal dependence in service processes are often found in multi-tier architectures and storage devices and must be captured accurately in capacity planning models...